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NXP Semiconductors
PRTR5V0U8S
Integrated octal low-capacity ESD protection
2. Pinning information
Table 1.
Pinning
Pin
1
2
Description
ESD protection I/O 1
ESD protection I/O 2
Simplified outline
10
6
Graphic symbol
3
4
5
6
7
8
ground (GND)
ESD protection I/O 3
ESD protection I/O 4
ESD protection I/O 5
ESD protection I/O 6
supply voltage (V CC )
1
2
3
10
9
8
9
ESD protection I/O 7
1
5
4
7
10
ESD protection I/O 8
3. Ordering information
5
001aah386
6
Table 2.
Ordering information
Type number
Package
Name
Description
Version
PRTR5V0U8S
TSSOP10
plastic thin shrink small outline package; 10 leads;
SOT552-1
body width 3 mm
4. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V (I/O-GND)
Parameter
input/output to
Conditions
Min
0
Max
5.5
Unit
V
ground voltage
V ESD
electrostatic
all pins; IEC 61000-4-2,
-
± 8
kV
discharge voltage
level 4; contact discharge
T stg
storage temperature
? 55
+125
° C
5. Recommended operating conditions
Table 4.
Operating conditions
Symbol
T amb
Parameter
ambient temperature
Conditions
Min
? 40
Typ
-
Max
+85
Unit
° C
PRTR5V0U8S
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 7 May 2010
? NXP B.V. 2010. All rights reserved.
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